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Si5023-EVB
typically expected at the limiting amplifier inputs
(typically 10 mV PP for the Si5023 device).
Jitter Generation : Referring to Figure 3, this test
requires a pattern generator, a clock source
(synthesizer signal source), a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50 ? ). During this test, there is no
modulation of the Data Clock; so, the data that is sent to
the CDR is jitter free. The Jitter Analyzer measures the
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer : Referring to Figure 3, this test requires
a pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50 ? ). During this test, the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
Pulse
Generator
Scope
DATAOUT–
Pattern
Analyzer
GPIB
2.5 V (Si5022)
or 3.3 V (Si5023)
+ –
REFCLK+
REFCLK–
+ REFCLK
– (optional)
DATAOUT
+
–
DATAOUT+
DATAIN+
+
–
DATAIN
CLKOUT
+
–
CLKOUT+
DATAIN–
Pattern
Generator
GPIB
Si5023-EVB
Data Clock+
CLKOUT–
Jitter
Analyzer
GPIB
Synthesizer
Modulation
GPIB
Clock
Signal Source
FM
Source
Figure 3. Test Configuration for Jitter Tolerance, Transfer, and Generation
4
Rev. 1.1
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